1. Field of the Invention
The present invention relates to a method of fabricating electronic devices of the type including a smoothing process using polishing. This invention is applicable to the production of various electronic materials in which A smoothing process is needed. For example, the invention is applicable to a process of fabricating semiconductor devices in which grooves or trenches formed in the surface of a substrate are filled up for planarization, and also to the manufacture of varies electronic devices such as magnetic disks in which smoothing is required.
2. Description of the Prior Art
In the production of electronic devices, smoothing must be achieved in various cases. For example, when grooves or trenches formed in the surface of a substrate are filled up with a filling material, the surface must be smoothed. In addition, the smoothing processes become necessary when a trench isolation, a trench capacitor or a metal wiring portion such as a connector plug is formed, and also when grooves or spaces are filled up to form a necessary part.
To accomplish the smoothing, various techniques using polishing have been considered. The term "polishing" used herein in a comprehensive sense, i.e., to broadly refer to any type of polishing process or system which is capable of accomplishing the smoothing process. Since the polishing is a mechanical means for smoothing an object, it is broadly applicable to various objects without substantial restriction and capable of exhibiting good smoothing accuracy. The polishing is, therefore, attractive and promising. One example of such smoothing processes using polishing is reported in The Nikkei Sangyo published Oct. 2, 1990, in which spherical nylon tools of 10 mm in diameter are used to polish away fine projections on a magnetic disk substrate with smoothing accuracy which is about 2.5 times as high as before.
However, when the polishing is employed to smoothing various electronic devices, we encounter various problems to be solved. A first problem is encountered when the polishing is effected after grooves or trenches in a substrate are filled up by means of a deposition process (such as the bias ECR-CVD, in particular) in which etching and deposition are achieved concurrently. In this instance, however, due to irregularity in height of the portions to be polished, the polishing can only be performed with insufficient accuracy. A second problem is the difficulty in determining a polish end.
The first problem will be discussed below in greater detail. The bias ECR-CVD or the like process which is capable of performing etching and deposition concurrently is an attractive technique. This is because such a deposition technique will promote micro-miniaturization of trench portions in conformity with an advance of the micro-miniaturization and integration of semiconductor devices, and also meet a demand for higher smoothing accuracies. As the miniaturizing and integration densities of semiconductor integrated circuits increase, the conventional selectively oxidized film (LOCOS) method used for isolating circuit elements has been replaced by the shallow trench method. In the shallow trench method, it is extremely effective if grooves or trenches are filled up by the bias ECR-CVD. The bias ECR-CVD accomplishes deposition and etching concurrently and, hence, is able to fill up wide and narrow trenches (grooves) with a filling material (an insulating material such as SiO.sub.2) of a same thickness, thus exhibiting a perfect shallow trenching. In addition, by controlling the ratio of the etching rate to the deposition rate, it is possible to fill up those trenches having a relatively large aspect ratio not less than 1.79, for example. With this control of the ratio of etching rate and deposition rate, lateral leveling can be used. The lateral leveling is a technique to perform deposition under the conditions that the etching proceeds in the lateral direction (parallel to the surface of a substrate), while in the vertical direction, neither etching nor deposition proceeds. Thus, etching is achieved selectively in the lateral direction. With this lateral leveling, it is possible to remove excess materials deposited on portions of the substrate other than those corresponding to trenches, thereby providing a margin or space necessary for a resist film registration or alignment.
The bias ECR-CVD method or the like deposition method described above is, however, still not fully satisfactory because of the drawbacks discussed below.
Since etching and deposition are achieved concurrently, the etching rate necessarily becomes small as a whole. Consequently, the throughput and productivity are relatively low. In addition, if the lateral leveling process is performed to provide a margin for resist registration, the throughput is reduced additional due to a small etching rate in the lateral direction.
With the foregoing drawbacks in view, an attempt has been made to remove an excess filling material (SiO.sub.2, for example) by polishing, but various problems have encountered in adopting the polishing process, as described below.
The deposition using the bias ECR-CVD method depends on the substrate. Accordingly, if the conventional bias ECR-CVD method is applied to fill up grooves (trenches) 21-23 in a surface of a substrate 1, as shown in FIG. 2B, a portion 31 of the filling material (SiO.sub.2) deposited on a wide land A is different in height from a portion 32 of the filling material deposited on a narrow land B. With this difference in height, these portions 31, 32 are subjected to polishing at different points of time. In addition, if the polishing has an angle dependency, the irregularity in deposition height largely affects the precision of polishing operation. Furthermore, in the bias ECR plasma CVD, in particular, due to a divergent magnetic field used in this process, the thickness of a filling material (SiO.sub.2, for example) becomes greater in a central portion of the substrate than in a peripheral portion of the substrate. The thickness irregularity thus produced will deteriorate the quality of the subsequent polishing operation.
A great interest has been shown toward application of the polishing techniques to silicon on insulator (SOI) technology, but any satisfactory solution has not been provided heretofore due to the difficulty in determining a polish end.